ON Semiconductor MC100LVE210FNG

Description
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed for clock distribution. It features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device has fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, reducing the skew between the two fundamental signals from a parttopart skew down to an outputtooutput skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task.

Features
200 ps ParttoPart Skew
50 ps Typical OutputtoOutput Skew
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: Vcc = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: Vcc = 0 V with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
PbFree and RoHS Compliant

Applications
High performance clock distribution in 3.3 V systems
Clock distribution across the backplane or the board
PECL mode operating range: Vcc = 3.0 V to 3.8 V with VEE = 0 V
NECL mode operating range: Vcc = 0 V with VEE = 3.0 V to 3.8 V