IDT, Integrated Device Technology Inc M1026-13-155.5200T

Description
The M1025/26 is a Voltage Controlled SAW Oscillator (VCSO) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. It is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. The device can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode.

Features
Integrated SAW delay line; low phase jitter of < 0.5psrms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz (Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively selected reference input
Hitless Switching (HS) options with or without Phase Build-out (PBO) to enable SONET (GR-253)/SDH (G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package

Applications
Clock jitter attenuation
Frequency translation
Transmit reference clock generation for optical network systems
Stratum reference clock jitter attenuation
Recovered clock jitter attenuation in loop timing mode