Linear Technology LTC2261CUJ-12#TRPBF
- Part Number:
- LTC2261CUJ-12#TRPBF
- Manufacturer:
- Linear Technology
- Ventron No:
- 3015452-LTC2261CUJ-12#TRPBF
- Description:
- IC ADC 12BIT 125MSPS 40-QFN
- Datasheet:
- LTC2261CUJ-12#TRPBF
Description
The LTC2261-12/LTC2260-12/LTC2259-12 are 12-bit, 125/105/80Msps ultralow power 1.8V ADCs designed for digitizing high-frequency, wide dynamic range signals. They are ideal for demanding communications applications with AC performance that includes 70.8dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17pSRMS allows undersampling of IF frequencies with excellent noise performance.
DC specs include 0.3LSB INL (typical), ±0.1LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.
The digital outputs can be either full-rate CMOS, double-data rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.
The ENC and ENC inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
Features
Low Power: 124mW/103mW/87mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1Vp.p to 2Vp.p
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm x 6mm) QFN Package
Applications
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
The LTC2261-12/LTC2260-12/LTC2259-12 are 12-bit, 125/105/80Msps ultralow power 1.8V ADCs designed for digitizing high-frequency, wide dynamic range signals. They are ideal for demanding communications applications with AC performance that includes 70.8dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17pSRMS allows undersampling of IF frequencies with excellent noise performance.
DC specs include 0.3LSB INL (typical), ±0.1LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.
The digital outputs can be either full-rate CMOS, double-data rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.
The ENC and ENC inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
Features
Low Power: 124mW/103mW/87mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1Vp.p to 2Vp.p
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm x 6mm) QFN Package
Applications
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
Linear Technology LTC2261CUJ-12#TRPBF technical specifications, attributes, parameters and parts with similar specifications to Linear Technology LTC2261CUJ-12#TRPBF.
- Factory Lead Time18 Weeks
- Mounting TypeSurface Mount
- Package / Case40-WFQFN Exposed Pad
- Surface MountYES
- Operating Temperature0°C~70°C
- PackagingTape & Reel (TR)
- Published2013
- JESD-609 Codee3
- Part StatusActive
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations40
- Terminal FinishMatte Tin (Sn)
- SubcategoryAnalog to Digital Converters
- TechnologyCMOS
- Terminal PositionQUAD
- Terminal FormNO LEAD
- Peak Reflow Temperature (Cel)260
- Number of Functions1
- Supply Voltage1.8V
- Terminal Pitch0.5mm
- Time@Peak Reflow Temperature-Max (s)30
- Base Part NumberLTC2261
- Pin Count40
- JESD-30 CodeS-PQCC-N40
- Qualification StatusNot Qualified
- ConfigurationS/H-ADC
- Number of Bits12
- Input TypeDifferential
- ArchitecturePipelined
- Number of Inputs1
- Converter TypeADC, PROPRIETARY METHOD
- Reference TypeExternal, Internal
- Data InterfaceLVDS - Parallel, Parallel
- Voltage - Supply, Analog1.7V~1.9V
- Voltage - Supply, Digital1.7V~1.9V
- Number of Analog In Channels1
- Sampling Rate (Per Second)125M
- Output Bit CodeOFFSET BINARY, 2'S COMPLEMENT BINARY
- Linearity Error-Max (EL)0.0244%
- Sample and Hold / Track and HoldSAMPLE
- Ratio - S/H:ADC1:1
- Output FormatPARALLEL, WORD
- Length6mm
- Height Seated (Max)0.8mm
- Width6mm
- RoHS StatusROHS3 Compliant
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