Linear Technology LTC2153CUJ-12#PBF
- Part Number:
- LTC2153CUJ-12#PBF
- Manufacturer:
- Linear Technology
- Ventron No:
- 3014392-LTC2153CUJ-12#PBF
- Description:
- IC ADC 12BIT DUAL 310MSPS
- Datasheet:
- LTC2153CUJ-12#PBF
Description
The LTC2153-12 is a 12-bit, 310Msps analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic range signals. It is ideal for demanding communications applications, offering exceptional AC performance with 67.6dBFS SNR and 88dB SFDR. The 1.25GHz input bandwidth enables the ADC to undersample high frequencies with excellent performance. The latency is a mere six clock cycles.
DC specifications include a typical INL of 0.6LSB, DNL of 0.1LSB, and no missing codes over temperature. The transition noise is a low 0.6LSBRMS.
The digital outputs are double data rate (DDR) LVDS. The ENC and ENC- inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer ensures high performance at full speed for a wide range of clock duty cycles.
Features
67.6dBFS SNR
88dB SFDR
Low power: 378mW total
Single 1.8V supply
DDR LVDS outputs
1.32Vp.p input range
1.25GHz full power bandwidth
S/H
Optional clock duty cycle stabilizer
Low power sleep and nap modes
Serial SPI port for configuration
Pin-compatible 12-bit versions
40-lead (6mm x 6mm) QFN package
Applications
Communications
Cellular basestations
Software defined radios
Medical imaging
High definition video
Testing and measurement instruments
The LTC2153-12 is a 12-bit, 310Msps analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic range signals. It is ideal for demanding communications applications, offering exceptional AC performance with 67.6dBFS SNR and 88dB SFDR. The 1.25GHz input bandwidth enables the ADC to undersample high frequencies with excellent performance. The latency is a mere six clock cycles.
DC specifications include a typical INL of 0.6LSB, DNL of 0.1LSB, and no missing codes over temperature. The transition noise is a low 0.6LSBRMS.
The digital outputs are double data rate (DDR) LVDS. The ENC and ENC- inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer ensures high performance at full speed for a wide range of clock duty cycles.
Features
67.6dBFS SNR
88dB SFDR
Low power: 378mW total
Single 1.8V supply
DDR LVDS outputs
1.32Vp.p input range
1.25GHz full power bandwidth
S/H
Optional clock duty cycle stabilizer
Low power sleep and nap modes
Serial SPI port for configuration
Pin-compatible 12-bit versions
40-lead (6mm x 6mm) QFN package
Applications
Communications
Cellular basestations
Software defined radios
Medical imaging
High definition video
Testing and measurement instruments
Linear Technology LTC2153CUJ-12#PBF technical specifications, attributes, parameters and parts with similar specifications to Linear Technology LTC2153CUJ-12#PBF.
- Lifecycle StatusPRODUCTION (Last Updated: 2 weeks ago)
- Package / CaseQFN
- Number of Pins40
- Max Operating Temperature70°C
- Min Operating Temperature0°C
- InterfaceLVDS, Parallel
- Number of Bits12
- Number of Inputs1
- Sampling Rate310 Msps
- Number of A/D Converters1
- RoHS StatusRoHS Compliant
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