Linear Technology LTC1749IFW#PBF
- Part Number:
- LTC1749IFW#PBF
- Manufacturer:
- Linear Technology
- Ventron No:
- 3016223-LTC1749IFW#PBF
- Description:
- IC ADC 12BIT 80MSPS SMPL 48TSSOP
- Datasheet:
- LTC1749IFW#PBF
Description
The LTC1749 is an 80Msps, 12-bit analog-to-digital converter (ADC) designed for digitizing wide dynamic range signals up to frequencies of 500MHz. It features a highly linear sample-and-hold circuit with a bandwidth of 500MHz and ultralow jitter of 0.15pSRMS, allowing for undersampling of IF frequencies with minimal degradation in SNR. The input range of the ADC can be optimized with the on-chip PGA sample-and-hold circuit and flexible reference circuitry. The digital interface is compatible with 5V, 3V, 2V, and LVDS logic systems. The LTC1749 is packaged in a 48-pin TSSOP package with a flow-through pinout.
Features
Sample Rate: 80Msps
PGA Front End (2.25Vp.p or 1.35Vp.p Input Range)
71.8dB SNR and 87dB SFDR (PGA=0)
70.2dB SNR and 87dB SFDR (PGA = 1)
500MHz Full Power Bandwidth S/H
No Missing Codes
Single 5V Supply
Power Dissipation: 1.45W
Two Pin Selectable Reference Values
Data Ready Output
Clock
Pin Compatible 14-Bit 80Msps Device (LTC1750)
Applications
Direct IF Sampling
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Communications Test Equipment
Undersampling
The LTC1749 is an 80Msps, 12-bit analog-to-digital converter (ADC) designed for digitizing wide dynamic range signals up to frequencies of 500MHz. It features a highly linear sample-and-hold circuit with a bandwidth of 500MHz and ultralow jitter of 0.15pSRMS, allowing for undersampling of IF frequencies with minimal degradation in SNR. The input range of the ADC can be optimized with the on-chip PGA sample-and-hold circuit and flexible reference circuitry. The digital interface is compatible with 5V, 3V, 2V, and LVDS logic systems. The LTC1749 is packaged in a 48-pin TSSOP package with a flow-through pinout.
Features
Sample Rate: 80Msps
PGA Front End (2.25Vp.p or 1.35Vp.p Input Range)
71.8dB SNR and 87dB SFDR (PGA=0)
70.2dB SNR and 87dB SFDR (PGA = 1)
500MHz Full Power Bandwidth S/H
No Missing Codes
Single 5V Supply
Power Dissipation: 1.45W
Two Pin Selectable Reference Values
Data Ready Output
Clock
Pin Compatible 14-Bit 80Msps Device (LTC1750)
Applications
Direct IF Sampling
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Communications Test Equipment
Undersampling
Linear Technology LTC1749IFW#PBF technical specifications, attributes, parameters and parts with similar specifications to Linear Technology LTC1749IFW#PBF.
- Factory Lead Time16 Weeks
- Mounting TypeSurface Mount
- Package / Case48-TFSOP (0.240, 6.10mm Width)
- Surface MountYES
- Operating Temperature-40°C~85°C
- PackagingTube
- Published2004
- JESD-609 Codee3
- FeaturePGA
- Part StatusActive
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations48
- Terminal FinishMatte Tin (Sn)
- SubcategoryAnalog to Digital Converters
- TechnologyCMOS
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)250
- Number of Functions1
- Supply Voltage5V
- Terminal Pitch0.5mm
- Time@Peak Reflow Temperature-Max (s)40
- Base Part NumberLTC1749
- Pin Count48
- JESD-30 CodeR-PDSO-G48
- Qualification StatusNot Qualified
- Power Supplies5V
- ConfigurationS/H-ADC
- Number of Bits12
- Input TypeDifferential
- ArchitecturePipelined
- Number of Inputs1
- Converter TypeADC, PROPRIETARY METHOD
- Reference TypeExternal, Internal
- Data InterfaceParallel
- Sampling Rate80 MHz
- Voltage - Supply, Analog5V
- Number of Analog In Channels1
- Sampling Rate (Per Second)80M
- Output Bit CodeOFFSET BINARY, 2'S COMPLEMENT BINARY
- Linearity Error-Max (EL)0.0244%
- Sample and Hold / Track and HoldSAMPLE
- Ratio - S/H:ADC1:1
- RoHS StatusROHS3 Compliant
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