IDT, Integrated Device Technology Inc IDT5T9890NLI

Description
The IDT5T9890 is a 2.5V PLL clock driver designed for high-performance computing and data-communications applications. It features programmable skew, allowing outputs to lead or lag the reference input signal. The device has ten programmable skew outputs in five banks of two, plus a dedicated differential feedback. Skew is controlled through JTAG or I²C programming.
The clock driver can be configured through JTAG/I²C programming. An internal EEPROM allows users to save and restore the device's configuration. The feedback bank provides divide-by-functionality from 1 to 12 through JTAG or I²C programming, enabling frequency multiplication without using divided outputs for feedback. Each output bank also allows for a divide-by-functionality of 2 or 4.
The IDT5T9890 supports a user-selectable, single-ended or differential input to ten single-ended outputs. It acts as a translator from differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Each output bank can be individually configured to be either HSTL, eHSTL, 2.5V LVTTL, or 1.8V LVTTL, including the feedback bank. Each clock input can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or differential signals. The outputs can be synchronously enabled/disabled and synchronized with the positive or negative edge of the reference clock input.

Features
2.5V operation
5 pairs of programmable skew outputs
EEPROM programmable 2.5V
Programmable skew PLL clock driver
Low skew: 100ps all outputs at same interface level, 250ps all outputs at different interface levels
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
Internal non-volatile EEPROM
JTAG or I²C bus serial interface for programming
Hot insertable and over-voltage tolerant inputs
Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface
Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for each output bank
Selectable differential or single-ended inputs and ten single-ended outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle, all outputs at same interface level: <100ps cycle-to-cycle all outputs at different interface levels
Power-down mode
Lock indicator
Available in VFQFPN package

Applications
High-performance computing
Data-communications
Networking
Storage
Industrial automation