IDT, Integrated Device Technology Inc IDT23S09-1HPG8

Description
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer designed for high-speed clock distribution applications. It operates within a frequency range of 10 to 133MHz and features zero delay by aligning the phase between the incoming and output clocks. The device has two banks of outputs, one with five outputs and the other with four outputs, each with separate output enable control. It exhibits low output skew (<250ps) and low jitter (<200ps cycle-to-cycle). The IDT23S09 operates at 3.3V VDD and is spread spectrum compatible. It is available in SOIC and TSSOP packages.

Features
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
Distributes one clock input to one bank of five and one bank of four outputs
Separate output enable for each output bank
Output Skew <250ps
Low jitter <200 ps cycle-to-cycle
IDT23S09-1 for Standard Drive
IDT23S09-1H for High Drive
No external RC network required
Operates at 3.3V VDD
Spread spectrum compatible
Available in SOIC and TSSOP packages

Applications
High-speed clock distribution
Networking and telecommunications
Data storage
Industrial control
Test and measurement