IDT, Integrated Device Technology Inc IDT2305B-1HDC

Description
The IDT2305B is a high-speed phase-locked loop (PLL) clock buffer designed for high-speed clock distribution applications. It operates within a frequency range of 10 to 133MHz and features zero input-output delay, low jitter, and output skew less than 250ps. The IDT2305B accepts one reference input and drives out five low skew clocks. It has an on-chip PLL that locks to the input clock and provides feedback from the CLKOUT pad. In the absence of an input clock, the device enters power-down mode, drawing less than 25μA and tri-stating the outputs.

Features
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
3.3V ZERO DELAY CLOCK BUFFER
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew <250ps
Low jitter <175 ps cycle-to-cycle
50ps typical cycle-to-cycle jitter (15pF, 66MHz)
IDT2305B-1 for Standard Drive
IDT2305B-1H for High Drive
No external RC network required
Operates at 3.3V VDD
Power down model
Available in SOIC and TSSOP packages

Applications
High-speed clock distribution
Clock buffering
Phase-locked loop applications
Industrial and commercial applications