Description
ALTERA's FLEX 10KE embedded programmable logic devices (PLDs) offer system-on-a-programmable-chip (SOPC) integration in a single device. They feature an enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions, with dual-port capability and up to 16-bit width per embedded array block (EAB). The logic array provides general logic functions.
Features
High density: 30,000 to 200,000 typical gates
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
MultiVolt™ I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
Low power consumption
Bidirectional I/O performance (sy and fco) up to 212 MHz
Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
-1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
Built-in Joint Test Action Group (ITAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
Applications
System-on-a-chip (SOC) designs
Embedded control systems
Data communications
Industrial automation
Consumer electronics
ALTERA's FLEX 10KE embedded programmable logic devices (PLDs) offer system-on-a-programmable-chip (SOPC) integration in a single device. They feature an enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions, with dual-port capability and up to 16-bit width per embedded array block (EAB). The logic array provides general logic functions.
Features
High density: 30,000 to 200,000 typical gates
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
MultiVolt™ I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
Low power consumption
Bidirectional I/O performance (sy and fco) up to 212 MHz
Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
-1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
Built-in Joint Test Action Group (ITAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
Applications
System-on-a-chip (SOC) designs
Embedded control systems
Data communications
Industrial automation
Consumer electronics
Altera EPF10K50EFI484-3 technical specifications, attributes, parameters and parts with similar specifications to Altera EPF10K50EFI484-3.
- Mounting TypeSurface Mount
- Package / Case484-BBGA
- Surface MountYES
- Operating Temperature-40°C~85°C TA
- PackagingTray
- SeriesFLEX-10KE®
- JESD-609 Codee0
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)3 (168 Hours)
- Number of Terminations484
- Terminal FinishTin/Lead (Sn/Pb)
- HTS Code8542.39.00.01
- SubcategoryField Programmable Gate Arrays
- TechnologyCMOS
- Voltage - Supply2.3V~2.7V
- Terminal PositionBOTTOM
- Terminal FormBALL
- Peak Reflow Temperature (Cel)220
- Supply Voltage2.5V
- Terminal Pitch1mm
- Reach Compliance Codecompliant
- Time@Peak Reflow Temperature-Max (s)30
- JESD-30 CodeS-PBGA-B484
- Number of Outputs254
- Qualification StatusNot Qualified
- Power Supplies2.52.5/3.3V
- Number of I/O220
- Propagation Delay13.5 ns
- Number of Inputs254
- Organization254 I/O
- Programmable Logic TypeLOADABLE PLD
- Number of Logic Elements/Cells2880
- Total RAM Bits40960
- Number of Gates199000
- Number of LABs/CLBs360
- Output FunctionMIXED
- Length23mm
- Height Seated (Max)2.1mm
- Width23mm
- RoHS StatusNon-RoHS Compliant
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