Cypress Semiconductor Corp CY2309CZXC-1

Description
The CY2305C and CY2309C are 3.3 V zero delay buffers designed to distribute high-speed clocks. They are available in 16-pin SOIC or TSSOP packages (CY2309C) and an 8-pin SOIC package (CY2305C).
The CY2305C accepts one reference input and drives out five low-skew clocks. The CY2309C accepts one reference input and drives out nine low-skew clocks, grouped as 4 4 1.
Both devices have on-chip phase-locked loops (PLLs) that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.
The CY2309C has two banks of four outputs each that are controlled by the select inputs. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the outputs by the select inputs for chip and system testing purposes.
The CY2305C and CY2309C PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off. This results in less than 12.0 μA of current draw for commercial temperature devices and 25.0 μA for industrial and automotive-A temperature parts.
The CY2309C PLL shuts down in one additional case: when S2:S1 is 1:0. In this case, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves as a non-zero delay buffer in this mode and the outputs are not three-stated.

Features
10 MHz to 100-133 MHz operating range
Zero input and output propagation delay
Multiple low skew outputs
One input drives five outputs (CY2305C)
One input drives nine outputs, grouped as 4 4 1 (CY2309C)
50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Test mode to bypass phase locked loop (PLL) (CY2309C) only
Available in space-saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
3.3 V operation
Commercial, industrial and automotive-A flows available

Applications
Clock distribution
Clock buffering
System timing
Test and measurement