Cypress Semiconductor Corp CY2305SC-1

Description
The CY2305/CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks. It accepts one reference input and drives out multiple low-skew clocks. The CY2305 has five outputs, while the CY2309 has nine outputs, grouped as 4 4 1.
The CY2305/CY2309 has on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309 has two banks of four outputs each, which can be controlled by the Select inputs.
The CY2305/CY2309 PLLs enter a power down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 μA current draw.

Features
10MHz to 100-/133 MHz operating range, compatible with CPU and PCI bus frequencies
Zero input-output propagation delay
60 ps typical cycle-to-cycle jitter (high drive)
Multiple low-skew outputs
85 ps typical output-to-output skew
One input drives five outputs (CY2305)
One input drives nine outputs, grouped as 4 4 1 (CY2309)
Compatible with Pentium-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309 only)
Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305)
3.3V operation
Industrial temperature available

Applications
Clock distribution in high-speed systems
PCI bus clock distribution
CPU clock distribution
Test and measurement equipment
Data acquisition systems