Texas Instruments CDCP1803RTHT

Description
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50Q transmission lines.
The CDCP1803 has three control terminals, SO, S1, and S2, to select different output mode settings. The CDCP1803 is characterized for operation from 40°C to 85°C.
For use in singleended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a commonmode voltage reference.

Features
Distributes one differential clock input to three LVPECL differential clock outputs
Programmable output divider for two LVPECL outputs
Lowoutput skew 15 ps (Typical)
Vcc Range 3 V3.6 V
Signaling Rate Up to 800MHz LVPECL
Differential Input Stage for Wide CommonMode Range
Provides VBB Bias Voltage Output for SingleEnded Input Signals
Receiver Input Threshold £75 mV
24Terminal QFN Package (4 mm x 4 mm)
Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL2, and SingleEnded: LVTTL/LVCMOS

Applications
Clock distribution
Data communications
Networking
Test and measurement
Industrial control