Texas Instruments CDCLVP2102RGTR

Description
The CDCLVP2102 is a versatile, low additive jitter buffer that generates four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for various communication applications. It has a maximum clock frequency of 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making it suitable for demanding applications.
The CDCLVP2102 clock buffer distributes two clock inputs (INO, IN1) to four pairs of differential LVPECL clock outputs (OUTO, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is designed for driving 50ohm transmission lines. When driving the inputs in singleended mode, the LVPECL bias voltage (VAC REF) should be applied to the unused negative input pin. However, for highspeed performance up to 2 GHz, differential mode is strongly recommended.

Features
Dual 1:2 differential buffer
Two clock inputs
Four LVPECL outputs
Maximum clock frequency: 2 GHz
Maximum core current consumption: 48 mA
Very low additive jitter: <100 fs, rms in 10kHz to 20MHz offset range
2.375V to 3.6V device power supply
Maximum propagation delay: 450 ps
Maximum within bank output skew: 10 ps
LVPECL reference voltage, VAC REF: available for capacitivecoupled inputs
Industrial temperature range: 40°C to 85°C
Available in 3mm × 3mm QFN16 (RGT) package
ESD protection exceeds 2 kV (HBM)

Applications
Wireless communications
Telecommunications/networking
Medical imaging
Test and measurement equipment