Analog Devices Inc. ADF4001BRU

Description
The ADF4001 clock generator is designed for implementing clock sources for PLLs requiring low noise and stable reference signals. It comprises a low noise digital PFD, a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. Additionally, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL can be implemented when the synthesizer is used with an external loop filter and VCO or VCXO. The N minimum value of 1 provides flexibility in clock generation.

Features
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (Ve) for Extended Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise

Applications
Clock Generation
200 MHz Clock Generator PLL
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM