Analog Devices Inc. AD9510BCPZ-REEL7

Description
The AD9510 is a multioutput clock distribution IC with an onchip PLL core. It emphasizes low jitter and phase noise for optimal data converter performance. The PLL section includes a programmable reference divider, low noise phase frequency detector, precision charge pump, and programmable feedback divider. By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz can be synchronized to the input reference.
There are eight independent clock outputs: four LVPECL (1.2 GHz) and four selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. Each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another can be adjusted using a divider phase select function. Two of the LVDS/CMOS outputs feature programmable delay elements with fullscale ranges up to 10 ns of delay.

Features
Low phase noise phaselocked loop core
Reference input frequencies to 250 MHz
Programmable dualmodulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCP) extends tuning range
Two 1.6 GHz, differential clock inputs
8 programmable dividers, 1 to 32, all integers
Phase select for outputtooutput coarse delay adjust
4 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 2 LVDS/CMOS outputs
Serial control port
Spacesaving 64lead LFCSP

Applications
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSS, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure