IDT, Integrated Device Technology Inc 8SLVP1208ANBGI

Description
The 8SLVP1208 is a highperformance differential LVPECL fanout buffer designed for fanning out highfrequency, low additive phasenoise clock and data signals. It operates from 3.3V and 2.5V power supplies and features:
Eight low skew, low additive jitter LVPECL output pairs
Two selectable differential clock input pairs that accept LVDS, LVPECL, and CML input levels
Maximum input clock frequency of 2GHz
LVCMOS interface levels for control input (input select)
Output skew of 28ps (typical)
Propagation delay of 410ps (maximum)
Low additive phase jitter (RMS: 54.1fs maximum)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption of 141mA
Available in leadfree (RoHS 6), 28Lead VFQFN package
40°C to 85°C ambient operating temperature

Features
Eight low skew, low additive jitter LVPECL output pairs
Two selectable differential clock input pairs
Maximum input clock frequency of 2GHz
LVCMOS interface levels for control input (input select)
Output skew of 28ps (typical)
Propagation delay of 410ps (maximum)
Low additive phase jitter (RMS: 54.1fs maximum)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption of 141mA
Available in leadfree (RoHS 6), 28Lead VFQFN package
40°C to 85°C ambient operating temperature

Applications
Clock distribution applications demanding welldefined performance and repeatability
Differential PCLKO, nPCLKO, PCLK1, and nPCLK1 pairs can also accept singleended LVCMOS levels