IDT, Integrated Device Technology Inc 8SLVD1208NBGI8

Description
The IDT8SLVD12081 is a highperformance differential LVDS fanout buffer designed for the fanout of highfrequency, very low additive phasenoise clock and data signals. It operates from a 2.5V power supply and features guaranteed outputtooutput and parttopart skew characteristics, making it ideal for clock distribution applications demanding welldefined performance and repeatability. The device has two selectable differential inputs and eight low skew outputs. The integrated bias voltage reference enables easy interfacing of singleended signals to the device inputs. The IDT8SLVD12081 is optimized for low power consumption and low additive phase noise.

Features
Eight low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
Maximum input clock frequency: 2GHz (maximum)
LVCMOS/LVTTL interface levels for the control input (input select)
Output skew: 8ps (typical)
Propagation delay: 255ps (typical)
Low additive phase jitter, RMS: FREF=156.25MHz, Vpp = 1V, 10kHz20MHz: 65fs (typical)
Maximum device current consumption (lop): 170mA
2.5V supply voltage
Leadfree (RoHS 6), 28Lead VFQFN packaging
40°C to 85°C ambient operating temperature

Applications
Clock distribution
Data distribution
Highspeed data transmission
Telecommunications
Networking
Test and measurement