IDT, Integrated Device Technology Inc 8737AG-11LFT

Description
The 873711 is a low skew, highperformance Differentialto3.3V LVPECL Clock Generator/Divider. It has two selectable clock inputs: CLK, nCLK (differential) and PCLK, NPCLK (LVPECL, CML, or SSTL). The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion. Guaranteed output and parttopart skew characteristics make the 873711 ideal for clock distribution applications demanding welldefined performance and repeatability.

Features
2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs
Selectable differential CLK, CLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
Maximum output frequency: 650MHz
Translates any singleended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
Output skew: 60ps (maximum)
Parttopart skew: 200ps (maximum)
Bank skew: Bank A 20ps (maximum), Bank B 35ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
Propagation delay: 1.7ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
LeadFree package RoHS compliant

Applications
Clock distribution
Clock synthesis
Clock buffering
Clock conditioning
Clock fanout