NXP USA Inc. 74LV573PW,112
Part Number:
- 74LV573PW,112
Manufacturer:
- NXP USA Inc.
Ventron No:
- 3219185-74LV573PW,112
Description:
- IC OCTAL D TRANSP LATCH 20TSSOP
Datasheet:
- 74LV573
Payment:
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Part Overview
Description
The 74LV573 is an octal D-type transparent latch with 3-state outputs. It is pin and function compatible with the 74HC573 and 74HCT573. The 74LV573 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches.
Features
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between Vcc 2.7 V and Voc = 3.6 V
Typical output ground bounce <0.8 V at Vcc = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at Vcc = 3.3 V and Tamb = 25 °C
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Common 3-state output enable input
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to 85 °C and from -40 °C to 125 °C
Applications
Bus-oriented applications
Input or output port for microprocessors
Data storage and retrieval
Control and timing circuits
The 74LV573 is an octal D-type transparent latch with 3-state outputs. It is pin and function compatible with the 74HC573 and 74HCT573. The 74LV573 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches.
Features
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between Vcc 2.7 V and Voc = 3.6 V
Typical output ground bounce <0.8 V at Vcc = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at Vcc = 3.3 V and Tamb = 25 °C
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Common 3-state output enable input
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to 85 °C and from -40 °C to 125 °C
Applications
Bus-oriented applications
Input or output port for microprocessors
Data storage and retrieval
Control and timing circuits
Specifications
NXP USA Inc. 74LV573PW,112 technical specifications, attributes, parameters and parts with similar specifications to NXP USA Inc. 74LV573PW,112.
- Mounting TypeSurface Mount
- Package / Case20-TSSOP (0.173, 4.40mm Width)
- Surface MountYES
- Operating Temperature-40°C~125°C
- PackagingTube
- Published2009
- Series74LV
- JESD-609 Codee4
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Number of Terminations20
- Terminal FinishNickel/Palladium/Gold (Ni/Pd/Au)
- Additional FeatureBROADSIDE VERSION OF 373
- SubcategoryFF/Latches
- TechnologyCMOS
- Voltage - Supply1V~5.5V
- Terminal PositionDUAL
- Terminal FormGULL WING
- Peak Reflow Temperature (Cel)260
- Number of Functions1
- Supply Voltage3.3V
- Terminal Pitch0.65mm
- Reflow Temperature-Max (s)30
- Base Part Number74LV573
- Pin Count20
- JESD-30 CodeR-PDSO-G20
- Qualification StatusNot Qualified
- Output TypeTri-State
- Circuit8:8
- Supply Voltage-Max (Vsup)5.5V
- Power Supplies3.3V
- Supply Voltage-Min (Vsup)1V
- Load Capacitance50pF
- Number of Ports2
- Number of Bits8
- FamilyLV/LV-A/LVX/H
- Output Characteristics3-STATE
- Current - Output High, Low16mA 16mA
- Logic TypeD-Type Transparent Latch
- Output PolarityTRUE
- Max I(ol)0.008 A
- Independent Circuits1
- Delay Time - Propagation24ns
- Length6.5mm
- Width4.4mm
- RoHS StatusROHS3 Compliant
Certification
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