Nexperia USA Inc. 74AVC1T1022GUX

Description
The 74AVC1T1022 is a 1to4 fanout buffer with dual supplies (VCCA and VCC(B)) for voltage translation. It has a data input (A), four data outputs (1Yn and 2Yn), and an output enable input (OE). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V, making the device suitable for low voltage translation between various voltage levels. The levels of A, OE, and 1Yn are referenced to VCC(A), while outputs 2Yn are referenced to VCC(B). This supply configuration allows two of the fannedout signals to be used in level shifting. A HIGH on OE causes all outputs to be pulled LOW via pulldown resistors, while a LOW on OE disconnects the pulldown resistors and enables all outputs. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The loff circuitry disables the output, preventing any damaging backflow current through the device when it is powered down.

Features
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD812 (0.8 V to 1.3 V)
JESD811 (0.9 V to 1.65 V)
JESD87 (1.2 V to 1.95 V)
JESD85 (1.8 V to 2.7 V)
JESD8B (2.7 V to 3.6 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS001 Class 3B exceeds 8 kV
CDM JESD22C101E exceeds 1000 V
Maximum data rates:
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 2.5 V translation)
200 Mbit/s (≥ 1.1 V to 1.8 V translation)
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Latchup performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Specified from 40 °C to 85 °C and 40 °C to 125 °C

Applications
Clock distribution
Level shifting
Fanout buffering