NXP USA Inc. 74ABT573AD,118
Part Number:
- 74ABT573AD,118
Manufacturer:
- NXP USA Inc.
Ventron No:
- 3219184-74ABT573AD,118
Description:
- IC OCTAL D TRANSP LATCH 20-SOIC
Datasheet:
- 74ABT573A
Payment:
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Part Overview
Description
The 74ABT573A is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74ABT573A is functionally identical to the 74ABT373 but has a flow-through pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
Features
74ABT573A is flow-through pinout version of 74ABT373
Inputs and outputs on opposite side of package allow easy interface to microprocessors
3-State output buffers
Common output enable
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
Power-up 3-State
Power-up reset
Applications
Bus interface
Data storage
Register file
Microprocessor interface
The 74ABT573A is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74ABT573A is functionally identical to the 74ABT373 but has a flow-through pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
Features
74ABT573A is flow-through pinout version of 74ABT373
Inputs and outputs on opposite side of package allow easy interface to microprocessors
3-State output buffers
Common output enable
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
Power-up 3-State
Power-up reset
Applications
Bus interface
Data storage
Register file
Microprocessor interface
Specifications
NXP USA Inc. 74ABT573AD,118 technical specifications, attributes, parameters and parts with similar specifications to NXP USA Inc. 74ABT573AD,118.
- Mounting TypeSurface Mount
- Package / Case20-SOIC (0.295, 7.50mm Width)
- Supplier Device Package20-SO
- Operating Temperature-40°C~85°C
- PackagingTape & Reel (TR)
- Series74ABT
- Part StatusObsolete
- Moisture Sensitivity Level (MSL)1 (Unlimited)
- Voltage - Supply4.5V~5.5V
- Output TypeTri-State
- Circuit8:8
- Current - Output High, Low32mA 64mA
- Logic TypeD-Type Transparent Latch
- Independent Circuits1
- Delay Time - Propagation3.3ns
- RoHS StatusROHS3 Compliant
Certification
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