TSMC’s CoWoS Advanced Packaging: Demand Soaring, Capacity Tight!

Against the background of the rapid development of artificial intelligence, the demand for high-performance AI chips is becoming increasingly tight. However, the production capacity of the related CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technology is in short supply, becoming a bottleneck restricting the supply of AI chips. Faced with this challenge, while accelerating production, major AI chip manufacturers are also actively seeking breakthroughs in other advanced packaging technologies to alleviate the problem of insufficient supply of AI chips.

Cloud AI Infrastructure Investment Soars, TSMC CoWoS Packaging Capacity Faces Challenges

According to Trendforce, large cloud service providers such as Microsoft, Google, Amazon and Meta are actively expanding their artificial intelligence infrastructure, with total investment expected to reach a staggering $170 billion this year. This trend has driven a surge in demand for AI chips, which in turn has led to an expansion of the silicon interposer area and a reduction in the number of chips that can be produced on a single 12-inch wafer. Therefore, TSMC’s CoWoS packaging production capacity continues to face supply shortage. In particular, as NVIDIA launches new B-series products including GB200, B100, and B200, it is expected to consume more CoWoS packaging capacity.

However, despite the continuous development of CoWoS packaging technology, it is still difficult to meet the growing demand for high-performance AI chips in the context of the explosive growth of AI. The main issues focus on the increase in chip size and the challenges of HBM stacking technology. The launch of Nvidia’s B200, B100 and other products has resulted in a significant expansion of the chip interposer area, which has reduced the number of chips cut from 12-inch wafers, further exacerbating the difficulty of CoWoS packaging technology in meeting the needs of AI chips. At the same time, as HBM technology continues to be iteratively updated, the number of DRAMs it covers is also increasing simultaneously, which is undoubtedly another major challenge for CoWoS packaging technology.

TSMC Urgently Increases Production of CoWoS Packaging Manufacturing Facility in Response to Surge in Demand for AI Chips

According to industry sources in Taiwan, China, TSMC has urgently placed an order for a large number of CoWoS packaging manufacturing equipment to expand its production capacity. Sources pointed out that TSMC has stated on multiple occasions that it expects AI servers to bring considerable revenue to the company in the next few years. Therefore, the company has recently adjusted its production capacity planning and placed orders for CoWoS-related equipment to the supply chain.

In addition, TSMC plans to expand production facilities to cope with huge demand. The company aims to triple CoWoS-based wafer production to produce 45,000 to 50,000 CoWoS-based wafers per month by the end of 2024. At the same time, the company also plans to double its SoIC-based wafer production capacity by the end of this year, expecting to produce 5,000 to 6,000 units per month. In the future, TSMC will maintain a continuous expansion model. It is expected that from the fourth quarter of 2024 to 2026, Longtan, Zhunan, Taichung, Tainan, Chiayi and the recently announced Chiayi AP7 fab will be put into operation one after another.

Core Issues Facing CoWoS Packaging Technology: HBM Chip Capacity and Technical Bottlenecks

CoWoS is an advanced three-dimensional integrated packaging technology developed by TSMC. This technology can be broken down into two parts to understand: CoW (Chip-on-Wafer) means chip stacking, while WoS (Wafer-on-Substrate) means packaging stacked chips on a substrate. Through this packaging technology, GPU and memory can be more closely connected. Its most important feature is the ability to significantly shorten the interconnection distance between the GPU and the HBM, resulting in faster data exchange while reducing power consumption and saving space.

Since CoWoS packaging technology involves the stacking of multiple chips such as HBM, CPU or GPU, this complex structure will take more time during the testing phase, resulting in increased testing costs. Industry experts point out that HBM chip production capacity is one of the key challenges for future development. The manufacturing process requires the use of EUV (extreme ultraviolet) lithography machines, and with the advancement of technology, the number of chip layers required to be manufactured gradually increases. Taking HBM market leader SK Hynix as an example, the company has already shifted from 1α process to 1β process and plans to significantly increase the application rate of EUV lithography, which is expected to be upgraded by 3 to 4 times. In addition, with the iterative updating of HBM technology, its storage capacity is also being increased in tandem, with the latest HBM4 technology expected to stack up to 16 layers of DRAM.

The semiconductor industry has also observed that silicon interposer area has continued to grow with each generation since the initial development of CoWoS technology in 2011, resulting in a reduction in the number of interposer wafers cut from 12-inch silicon wafers. At the same time, as the number of HBM memories mounted on chips has doubled and HBM standards continue to improve, the number of HBMs that need to be placed around GPUs has also increased, which is regarded by the industry as a bottleneck in current technological development.

NVIDIA Foresight Layout of FOPLP Technology to Address HBM Chip Capacity and Technical Challenges

Industry analysis points out that under the dual bottlenecks of CoWoS and HBM, the production capacity problem will be difficult to effectively solve in the short term. In order to alleviate the tight situation of CoWoS advanced packaging production capacity, TSMC’s competitor NVIDIA is planning to introduce its GB200 products into fan-out panel-level packaging (FOPLP) technology early, which is expected to be advanced from the original 2026 to 2025.

According to reports, the latest agency report also confirmed the relevant news and pointed out that the supply chain of Nvidia GB200 has been launched and is currently in the design fine-tuning and testing stage. From the CoWoS advanced packaging capacity study, it is expected that about 420,000 GB200 chips will be delivered to the downstream market in the second half of this year, while next year’s output is expected to be between 1.5 million and 2 million. Overall, with CoWoS production capacity in short supply, the industry generally expects that FOPLP, also an advanced packaging technology, is expected to become an effective means to ease the tight supply of AI chips.

With the rapid development of artificial intelligence technology, the demand for AI chips in data centers is surging at an unprecedented rate, which not only brings huge challenges to the semiconductor industry, but also breeds unprecedented opportunities. Against this background, the rise of advanced packaging technology has become the core driving force for the development of the semiconductor industry and the key to future competition in the semiconductor industry. As a global leader in semiconductor production, TSMC will continue to uphold the concepts of innovation and excellence, enhance its own technological strength and market competitiveness in the field of packaging, and contribute more to the prosperity and development of the semiconductor industry.