PTI Chairman believes that FOPLP is an alternative solution for IC scaling
28 August 2023
FOPLP (Fanout Panel-Level Package) will be a new option. It does not mean supporting nodes that are 7nm, 5nm or higher. Instead, it provides a package that can achieve IC scaling without expensive advanced manufacturing processes. solution. DK Tsai, chairman of Taiwan's back-end expert Powertech Technology (PTI).
Cai told Digitimes that in the foundry, the more advanced the process, the higher the performance of the fabricated chips. However, not every chip designer can afford the high cost of adopting advanced manufacturing nodes. As a result, FOPLP will be an alternative solution for chip manufacturers, enabling constant 2D scaling of HPC chipsets without the need for advanced process nodes.
Tsai goes on to say that fan-out packages can integrate the various functional components built using different process nodes to achieve the same performance of SoCs built on advanced nodes, making IC designers the most cost-effective solution.
He revealed that PTI has divided its engineers into two broad categories, one for packaging and the other for testing to address increasingly complex back-end technologies, including FOPLP. He said that heterogeneous integrated packaging for CPUs, WiFi chips, memory chips and other functional chips will be more difficult than testing.
Cai said that PTI's capital expenditure will increase from NT$10 billion in 2019 to NT$1.4-1.5 billion in 2020, and then further increase in 2021-2025 to support the development of more advanced back-end technologies.
He is confident that, with the exception of South Korea, most memory module manufacturers will rely on PTI to provide back-end services in 2020.
Cai told Digitimes that in the foundry, the more advanced the process, the higher the performance of the fabricated chips. However, not every chip designer can afford the high cost of adopting advanced manufacturing nodes. As a result, FOPLP will be an alternative solution for chip manufacturers, enabling constant 2D scaling of HPC chipsets without the need for advanced process nodes.
Tsai goes on to say that fan-out packages can integrate the various functional components built using different process nodes to achieve the same performance of SoCs built on advanced nodes, making IC designers the most cost-effective solution.
He revealed that PTI has divided its engineers into two broad categories, one for packaging and the other for testing to address increasingly complex back-end technologies, including FOPLP. He said that heterogeneous integrated packaging for CPUs, WiFi chips, memory chips and other functional chips will be more difficult than testing.
Cai said that PTI's capital expenditure will increase from NT$10 billion in 2019 to NT$1.4-1.5 billion in 2020, and then further increase in 2021-2025 to support the development of more advanced back-end technologies.
He is confident that, with the exception of South Korea, most memory module manufacturers will rely on PTI to provide back-end services in 2020.
